Current Issue : January-March Volume : 2022 Issue Number : 1 Articles : 5 Articles
This article uses Field Programmable Gate Array (FPGA) as a carrier and uses IP core to form a System on Programmable Chip (SOPC) English speech recognition system. The SOPC system uses a modular hardware system design method. Except for the independent development of the hardware acceleration module and its control module, the other modules are implemented by software or IP provided by Xilinx development tools. Hardware acceleration IP adopts a topThdown design method, provides parallel operation of multiple operation components, and uses pipeline technology, which speeds up data operation, so that only one operation cycle is required to obtain an operation result. In terms of recognition algorithm, a more effective training algorithm is proposed, Genetic Continuous Hidden Markov Model (GA_CHMM), which uses genetic algorithm to directly train CHMM model. It is to find the optimal model by encoding the parameter values of the CHMM and performing operations such as selection, crossover, and mutation according to the fitness function. The optimal parameter value after decoding corresponds to the CHMM model, and then the English speech recognition is performed through the CHMM algorithm. This algorithm can save a lot of training time, thereby improving the recognition rate and speed. This paper studies the optimization of embedded system software. By studying the fixedThpoint software algorithm and the optimization of system storage space, the realThtime response speed of the system has been reduced from about 10 seconds to an average of 220 milliseconds. Through the optimization of the CHMMalgorithm, the realThtime performance of the system is improved again, and the average time to complete the recognition is significantly shortened. At the same time, the system can achieve a recognition rate of over 90% when the English speech vocabulary is less than 200....
With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability....
The basic need common to all living beings is water. Less than 1% of the water on earth is fresh water and water use is increasing daily. Agricultural practices alone require huge amounts of water. The drip technique improved the efficiency of water use in irrigation and initiated the introduction and development of fertigation, the integrated distribution of water and fertilizer. The past few decades have seen extensive research being carried out in the area of development and evaluation of different technologies available to estimate/measure soil moisture to aid in various applications and to facilitate the use of drip irrigation for users and farmers. In this technology, plant moisture and temperature are accurately monitored and controlled in real time over roots in the form of droplets, by developing smart monitoring system to save water and avoid water waste using drip irrigation technology. Water is delivered to the roots drop by drop, which saves water as well as prevents plants from being flooded and decaying due to excess water released by irrigation methods such as flood irrigation, border irrigation, furrow irrigation, and control basin irrigation. Drip irrigation with an embedded intelligent monitoring system is one of the most valuable techniques used to save water and farmers’ time and energy. In this paper, we design an embedded monitoring system based in the integrated 65 nm CMOS technology in agricultural practices which would facilitate agriculture and enable farmers to monitor crops. Hence, to demonstrate the feasibility, a prototype was constructed and simulated with modelsim and validated with nclaunch the both tools from Cadence, as well as implementation on the FPGA board, was be performed....
The outage performance of a reconfigurable intelligent surface- (RIS-) aided full-duplex cooperative nonorthogonal multiple access (NOMA) system is studied in this paper. Based on the statistical characteristics of the signal-to-noise ratio of the reflection channel from the access point via RIS to the near user, and the cooperative channel from the near user to the far NOMA user, the outage probability of both the near and far users is derived. Through the comparison with the outage performance of conventional cooperative NOMA without employing RIS, the superiority of the proposed scheme is demonstrated. Finally, the correctness of the analytical results is validated with simulation....
A continuously reconfigurable metasurface reflector based on unit cell mushroom geometry that was integrated with a varactor diode is presented in this paper. The unit cell of the metasurface was designed and optimized to operate in the X-band and Ku-band, improving satellite communication’s quality of service. The losses mechanisms of continuous control over the unit cell phase reflection in beam steering resolution are considered and the analysis results are presented. The unit cell design parameters were analyzed with an emphasis on losses and dynamic reflection phase range. The unit cell magnitude and phase reflection are shown in the wide frequency bandwidth and showed a good agreement between all the measurements and the simulations. This metasurface enabled a high dynamic range in the unit cell resonant frequency range from 7.8 to 15 GHz. In addition, the reflection phase and absorption calibration are demonstrated for multiple operating frequencies, namely, 11 GHz, 12 GHz, and 13.5 GHz. Furthermore, design trade-offs and manufacturing limitations were considered. Finally, a beam-steering simulation using the designed metasurface is shown and discussed....
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